Expertise in SoC & Subsystems

IP, SoC Architecture Design

  • Architecture and Microarchitecure Development
  • RTL Design
  • SoC Integration
  • Performance Modeling
  • Tool Flow and Methodology


  • Setting up the Synthesis Flow
  • Developing Constraints
  • Logic and Physical Aware Synthesis

Static Timing Analysis

  • Setting up the STA flow
  • Timing Constraints generation for Multiple Modes
  • Timing Analysis for Multi Modes and Multi Corners
  • Timing ECOs using TSO or DMSA
  • SI Analysis

Functional Verification

  • SoC/ASIC/Subsystems/IP Functional Verification
  • Verification planning, feature extraction, capturing functional coverage and check points
  • Architecting Testbench & developing reusable verification environment
  • Assertion-based verification using SVA & and Formal Verification, Formal/Static Property based Verification
  • Metric & coverage driven verification
  • Processor/ARM Based SoC Verification
  • Creation of wrappers and multi-language interfaces adapters
  • Creation of reference models using traditional HDL languages and advanced HVL languages like System Verilog, C, C++ and System C
  • Automation and Regression management
  • Gate level simulation (GLS)
  • Register abstraction based flow enabling design and verification reuse
  • Development of Assertions and protocol checkers
  • Development of SystemC/TLM models of module and complete systems
  • End-to-end verification closure from specification to RTL signoff
  • Low-power verification– power estimation, CPF/UPF
  • Analog Mixed Signal Verification
  • Hardware & Software Co-verification
  • Verification IP Development and Verification
  • Pre-Silicon and Post-Silicon Validation/Verification
  • Simulator Development & EDA Tool Validation
  • Interoperability Testing


  • ASIC/SoC, FPGA, Model building, Validation
  • Complete SoC/ASIC Emulation on Emulation Platforms – Zebu, Palladium, Veloce
  • Design Partitioning, Synthesis, Integration, IO & Memory connection
  • Build DUT emulation environment
  • Connect HW monitor inside emulator
  • Performance analysis of DUT
  • Integration of Transactor based solution on Emulation board for protocols like Ethernet, PCIe and SATA and other protocols
  • Integration/porting of existing UVM/SV testbench on emulation setup
  • Test development and Debugging

Physical Design

  • Physical Design backend flow & methodology set up
  • RTL Integration, Synthesis/Formal equivalence/UPF flow/CLP checks
  • Floor-Planning /IO Planning/Power Planning/Place & Route
  • Clock Tree Synthesis
  • Setting up the Static Timing Analysis(STA) flow, STA & Design analysis
  • Physical Verification (design rule check (DRC), layout versus schematic (LVS), XOR (exclusive OR), antenna checks and electrical rule check (ERC))
  • Full Chip Design Partitioning, Timing optimization & Closure, & Signoff
  • Logical Equivalence Checks
  • Qualifying Libraries and Design Constraints
  • Power Planning, Low Power Strategy, & Low Power Implementation for Static/Dynamic reductions
  • Low Power Checks & Power Analysis (EM/IR)
  • Design For test (Scan insertion, LBIST, MBIST, ATPG) & Timing closure
  • X-talk noise and signal integrity
  • Design for Manufacturing (Metal Fill, Spare Cells, Decap Cells)
  • ECO fixes (Functional & Timing)
  • UPF/CPF flow development.
  • CAD/EDA Physical desing tools installation, LSF/EOD/License management
  • Expertise in 7nm, 14nm, 28nm and above.


  • DFT Architecture, Implementation and validation
  • Scan design architecture, Scan insertionand compression
  • ATPG Pattern Generation for various fault models (Stuck-at, Transition, Bridging and Cell aware Fault Model) and Fault Coverage Analysis
  • MBIST Implementation & Memory Testing
  • High test coverage with fault models, BIST for memory and logic
  • IO Testing using JTAG/Boundary SCAN Implementation and validation
  • DFX Validation at RTL and Gate Level
  • Analog BIST Simulations
  • Post Silicon debug, ATE Board design & bring up
  • Post-silicon ATE debug and support

CAD Tools Flow and Methodology

  • Infrastructure set up and Support
  • EDA Tools installation and integration
  • Back-End methodology flow set up
  • LSF/EOD/License management
  • Scripting and automation using Perl, Skill, TCL, Python and Shell etc.